I coded
1) small combinational logic cct.
2) Asynchronous counter
hope this will be help full all the test benches are available with the code try this with xilinx and leave your comments.
1) small combinational logic cct
code...........
module ExCombinational(
input a,
input b,
input c,
output x,
output y
);
wire e;
and g1(e,a,b);
not g2(y,c);
or(x,e,y);
endmodule
test bench...............................
module CombinationalcctTester(
);
wire t_x,t_y;
reg t_a,t_b,t_c;
ExCombinational CCC(.a(t_a),.b(t_b),.c(t_c),.x(t_x),.y(t_y));
initial
begin
$monitor(t_a,t_b,t_c,t_x,t_y);
t_a=1'b0;
t_b=1'b0;
t_c=1'b0;
#5
t_a=1'b0;
t_b=1'b0;
t_c=1'b1;
#5
t_a=1'b0;
t_b=1'b1;
t_c=1'b0;
#5
t_a=1'b0;
t_b=1'b1;
t_c=1'b1;
#5
t_a=1'b1;
t_b=1'b0;
t_c=1'b0;
#5
t_a=1'b1;
t_b=1'b0;
t_c=1'b1;
#5
t_a=1'b1;
t_b=1'b1;
t_c=1'b0;
#5
t_a=1'b1;
t_b=1'b1;
t_c=1'b1;
end
endmodule
2) Asynchronous counter
module AsCouter(clk,count);
input clk;
output[3:0] count;
wire clk;
reg[3:0] count;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule
test bench.........................
module ConterTest(
);
reg clk;
wire[3:0] count;
AsCouter mycounter(.clk(clk),.count(count));
initial
begin
clk=0;
#200 $finish;
end
always
begin
#2 clk=~clk;
end
always @( posedge clk)
$display("Count = %b", count );
endmodule
